?2011 fairchild semiconductor corporation www.fairchildsemi.com fd d24an06l a0_f085 n- c hannel logic level powertrench ? mo sf et 60v, 36a, 24m ? fea t ures ?r ds( o n) = 20m ? ( t yp.), v gs = 5v , i d = 3 6 a q g (t ot ) = 16nc (typ.), v gs = 5v l ow miller charge low q rr bod y diode uis capability (single pulse and repetitive pulse) qualified to aec q101 for mer l y developmental type 83547 ap p lications m o tor / body load control abs systems powertrain management injection systems dc-dc converters and off-line ups distributed power architectures and vrms primary switch for 12v and 24v systems mos fet maximum ratings t c = 25c u nless otherwise noted the rma l characteristics thi s product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. for a copy of the requirements, see aec q101 at: http://www.aec ounc il.com/ reliability data can be found at: http://www.fairchildsemi.com/pr oducts/discrete/reliability/index.html. all fairchild semiconductor products are manufactured, assembled and tested under iso 9000 and qs9000 quality systems certificatio n. sy m b ol parameter ratings units v dss dr ai n to source voltage 60 v v gs ga te to source voltage 20 v i d dr ai n current 40 a continuous (t c = 25 o c, v gs = 1 0 v) continuous (t c = 25 o c, v gs = 5v ) 3 6 a continuous (t c = 100 o c, v gs = 5v) 2 5 a c ontinuous (t a = 25 o c, v gs = 5v , r ja = 52 o c/w) 7 .1 a pulsed figure 4 a e as si ng le pulse avalanche energy (note 1) 32 mj p d pow e r dissipation 75 w derate above 25 o c0 . 5 w / o c t j , t stg op er ating and storage temperature -55 to 175 o c r jc the rmal resistance junction to case to-252 2.0 o c/w r ja the r mal resistance junction to ambient to-252 100 o c/w r ja ther mal resistance junction to ambient to-252, 1in 2 copp er pad area 52 o c/w d g s gat e so urce drain ( flange) to- 2 52aa fdd se rie s rohs compliant f dd 2 4 a n 0 6 l a0_f085 rev. c1 august 2 0 11 fdd24an06la0_f085 n-channel logic level powertrench ? mosfet
? 20 11 fa i r c h i l d s e m i c o n d u c t o r c o r p o r a t i o n www.fairchildsemi.com pack age marking and ordering information electrical characteristics t c = 25 c unless otherwise noted off c h aracteristics on characteristics dynamic characteristics switching characteristics (v gs = 5 v ) drain - source diode characteristics no t es: 1: starting t j = 25 c , l = 80 h, i as = 28 a. de v ice marking device package reel size tape width quantity fdd24an06la0 fdd24an06la0 to-252aa 330mm 16mm 2500 units symbol parameter test conditions min typ max units b vds s dr ai n to source breakdown voltage i d = 25 0 a, v gs = 0v 60 - - v i dss ze r o gate voltage drain current v ds = 5 0 v - - 1 a v gs = 0v t c = 15 0 o c- - 2 50 i gss g ate to source leakage current v gs = 20v - - 10 0 na v gs(t h ) ga t e to source threshold voltage v gs = v ds , i d = 250 a1 - 2v r ds(o n) dr ai n to source on resistance i d = 40 a , v gs = 10v - 0.016 0.019 ? i d = 36a, v gs = 5v - 0.020 0.024 i d = 36 a , v gs = 5 v , t j = 17 5 o c - 0. 0 47 0.056 c iss inp u t capacitance v ds = 2 5 v, v gs = 0v , f = 1mhz - 1850 - pf c oss ou t put capacitance - 180 - pf c rss re v erse transfer capacitance - 75 - pf q g(t o t) to ta l gate charge at 5v v gs = 0 v to 5v v dd = 3 0v i d = 36 a i g = 1. 0m a 16 21 nc q g(t h ) th r eshold gate charge v gs = 0 v to 1v - 1.8 2.4 nc q gs ga te to source gate charge - 6.3 - nc q gs2 ga t e charge threshold to plateau - 4.5 - nc q gd g ate to drain ?miller? charge - 5.0 - nc t on tu rn -on time v dd = 30 v , i d = 36 a v gs = 5v, r gs = 9.1 ? --195ns t d(o n ) tu rn -on delay time - 12 - ns t r ri se time - 118 - ns t d( o ff) tu rn -off delay time - 26 - ns t f fal l time - 41 - ns t off tu rn -off time - - 101 ns v sd so ur ce to drain diode voltage i sd = 36a - - 1.25 v i sd = 18 a - - 1.0 v t rr rev e rse recovery time i sd = 36 a, di sd /dt = 1 00a/ s- - 34ns q rr re verse recovered charge i sd = 36a, di sd /d t = 100a/ s- - 30nc f dd 2 4 a n 0 6 l a0_f085 rev. c1 fdd24an06la0_f085 n-channel logic level powertrench ? mosfet
? 20 11 fa i r c h i l d s e m i c o n d u c t o r c o r p o r a t i o n t ypical characteristics t c = 25c unless otherwise noted fi gure 1. normalized power dissipation vs ambient temperature figure 2. maximum continuous drain current vs case temperature figure 3. normalized maximum transient thermal impedance figure 4. peak current capability t c , cas e temperature ( o c) p ower dissipation multiplier 0 0 25 50 75 100 175 0.2 0.4 0.6 0.8 1.0 1.2 125 150 0 10 20 30 40 50 25 50 75 100 125 150 175 i d , drain curre nt (a) t c , case temperature ( o c) v gs = 1 0v v gs = 5 v 0.01 0. 1 1 10 -4 10 -3 10 -2 10 -1 10 0 10 1 2 10 -5 t , rectangular pulse duration (s) z jc , no rmalized thermal impedance n otes: duty factor: d = t 1 /t 2 p eak t j = p dm x z jc x r jc + t c p dm t 1 t 2 0.5 0.2 0.1 0.05 0.01 0.02 dut y cycle - descending order si ngle pulse 10 0 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 30 400 i dm , p eak current (a) t , pulse width (s) t c = 2 5 o c i = i 25 175 - t c 15 0 f or temperatures above 25 o c de rate peak curre nt as follows: t ransconductance may limit current in this region v gs = 10v v gs = 5 v www.fairchildsemi.com f dd 2 4 a n 0 6 l a0_f085 rev. c1 fdd24an06la0_f085 n-channel logic level powertrench ? mosfet
? 20 11 fa i r c h i l d s e m i c o n d u c t o r c o r p o r a t i o n fi gure 5. forward bias safe operating area n ote: refer to fairchild application notes an7514 and an7515 fi gure 6. unclamped inductive switching capability figure 7. transfer characteristics figure 8. saturation characteristics figure 9. drain to source on resistance vs gate voltage and drain current figure 10. normalized drain to source on resistance vs junction temperature t ypical characteristics t c = 25c unless otherwise noted 0.1 1 10 100 100 0 11 01 0 0 v ds , drain t o source voltage (v) i d , drain curre nt (a) t j = m ax rated t c = 2 5 o c si ngle pulse li mited by r ds (on) are a may be operation in this 10 s 1m s dc 100 s 10m s 1 10 100 0.001 0.01 0.1 1 10 10 0 i as , avalanche current (a) t av , time in avalanche (ms) s tarting t j = 2 5 o c s tarting t j = 150 o c t av = (l)(i as ) /(1.3*rated bv ds s - v dd ) if r = 0 if r 0 t av = (l/r)ln[(i as * r)/(1.3*rated bv ds s - v dd ) + 1] 0 15 30 45 60 12 34 i d , drain curre nt (a) v gs , g ate to source voltage (v) p ulse duration = 80 s duty cycle = 0.5% max v dd = 1 5v t j = 175 o c t j = 2 5 o c t j = - 55 o c 0 15 30 45 60 0 0 .5 1.0 1.5 2.0 i d , drain curre nt (a) v ds , drain t o source voltage (v) v gs = 3 v pu lse duration = 80 s duty cycle = 0.5% max t c = 2 5 o c v gs = 10v v gs = 3.5v v gs = 5 v 10 20 30 40 50 246 81 0 i d = 5 a v gs , gate to source voltage (v) i d = 40a r ds (on) , drain t o source on resistance (m ? ) p ulse duration = 80 s duty cycle = 0.5% max 0 0.5 1.0 1.5 2.0 2.5 - 80 -40 0 40 80 120 160 200 no rmalized drain to source t j , j unction temperature ( o c) o n resistance v gs = 10v, i d = 40a p ulse duration = 80 s duty cycle = 0.5% max www.fairchildsemi.com f dd 2 4 a n 0 6 l a0_f085 rev. c1 fdd24an06la0_f085 n-channel logic level powertrench ? mosfet
? 20 11 fa i r c h i l d s e m i c o n d u c t o r c o r p o r a t i o n fi gure 11. normalized gate threshold voltage vs junction temperature figure 12. normalized drain to source breakdown voltage vs junction temperature figure 13. capacitance vs drain to source voltage figure 14. gate charge waveforms for constant gate current t ypical characteristics t c = 25c unless otherwise noted 0.25 0.50 0.75 1.00 1.25 - 80 -40 0 40 80 120 160 200 v gs = v ds , i d = 250 a no rmalized gate t j , j unction temperature ( o c) t hreshold voltage 0.90 0.95 1.00 1.05 1.10 - 80 -40 0 40 80 120 160 200 t j , j unction temperature ( o c) no rmalized drain to source i d = 250 a b reakdown voltage 100 1000 0. 1 1 10 60 40 2500 c, cap acitance (pf) v ds , drain to source voltage (v) v gs = 0 v, f = 1mhz c i ss = c gs + c gd c os s ? c ds + c gd c r ss = c gd 0 2 4 6 8 10 0 5 10 15 20 25 30 v gs , g ate to source voltage (v) q g , g ate charge (nc) v dd = 30v i d = 36a i d = 5 a waveforms in descending order: www.fairchildsemi.com f dd 2 4 a n 0 6 l a0_f085 rev. c1 fdd24an06la0_f085 n-channel logic level powertrench ? mosfet
? 20 11 fa i r c h i l d s e m i c o n d u c t o r c o r p o r a t i o n t est circuits and waveforms f igure 15. unclamped energy test circuit figure 16. unclamped energy waveforms figure 17. gate charge test circuit figure 18. gate charge waveforms figure 19. switching time test circuit figure 20. switching time waveforms t p v gs 0. 01 ? l i as + - v ds v dd r g dut va ry t p t o obtain required peak i as 0v v dd v ds bv ds s t p i as t av 0 v gs + - v ds v dd dut i g( ref) l v dd q g( th) v gs = 1 v q gs2 q g( tot) v gs = 5 v v ds v gs i g( ref) 0 0 q gs q gd v gs r l r gs dut + - v dd v ds v gs t on t d( on) t r 90% 10% v ds 90% 10% t f t d( off) t of f 90% 50% 50% 10% pu lse width v gs 0 0 www.fairchildsemi.com f dd 2 4 a n 0 6 l a0_f085 rev. c1 fdd24an06la0_f085 n-channel logic level powertrench ? mosfet
? 20 11 fa i r c h i l d s e m i c o n d u c t o r c o r p o r a t i o n t hermal resistance vs. mounting pad area t he maximum rated junction temperature, t jm , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, p dm , in an application. therefore the application?s ambient temperature, t a ( o c ), and thermal resistance r ja ( o c/ w) must be reviewed to ensure that t jm is never exceeded. equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. in using surface mount devices such as the to-252 package, the environment in which it is applied will have a significant influence on the part?s current and maximum power dissipation ratings. precise determination of p dm is c omplex and influenced by many factors: 1. mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. the number of copper layers and the thickness of the board. 3. the use of external heat sinks. 4. the use of thermal vias. 5. air flow and board orientation. 6. for non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. fairchild provides thermal information to assist the designer?s preliminary application evaluation. figure 21 defines the r ja f or the device as a function of the top copper (component side) area. this is for a horizontally positioned fr-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. this graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. pulse applications can be evaluated using the fairchild device spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. thermal resistances corresponding to other copper areas can be obtained from figure 21 or by calculation using equation 2 or 3. equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square. the area, in square inches or square centimeters is the top copper area including the gate and source pads. (eq. 1) p dm t jm t a ? () r ja --- -------------------------- = a rea in inches squared (eq . 2) r ja 33 .32 23.84 0.268 area + () ------------------------------------ - + = (eq . 3) r ja 33 .32 154 1.73 area + () --------------------------------- - + = a rea in centimeters squared 25 50 75 10 0 125 0.01 0.1 1 10 (0.645) (6.45) (64.5) (0.0645) fi gure 21. thermal resistance vs mounting pad area r ja = 33.32+ 23.84/(0.268+area) eq.2 r ja ( o c/w ) are a, top copper area in 2 (c m 2 ) r ja = 33.32+ 154/(1.73+area) eq.3 www.fairchildsemi.com f dd 2 4 a n 0 6 l a0_f085 rev. c1 fdd24an06la0_f085 n-channel logic level powertrench ? mosfet
trademarks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume an y liability arising out of the application or use of any product or circuit described herein; neither does it convey an y license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized for use as critical co mponents in life support devices or systems without the express written approval of fa irchild semiconductor corporation. as used here in: 1. life support devices or systems ar e devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signi ficant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms 2cool? accupower? auto-spm? ax-cap?* bitsic ? build it now? coreplus? corepower? crossvolt ? ctl? current transfer logic? deuxpeed ? dual cool? ecospark ? efficentmax? esbc? fairchild ? fairchild semiconductor ? fact quiet series? fact ? fast ? fastvcore? fetbench? flashwriter ? * fps? f-pfs? frfet ? global power resource sm green fps? green fps? e-series? g max ? gto? intellimax? isoplanar? megabuck? microcoupler? microfet? micropak? micropak2? millerdrive? motionmax? motion-spm? mwsaver? optihit? optologic ? optoplanar ? ? pdp spm? power-spm? powertrench ? powerxs? programmable active droop? qfet ? qs? quiet series? rapidconfigure? saving our world, 1mw/w/kw at a time? signalwise? smartmax? smart start? spm ? stealth? superfet ? supersot?-3 supersot?-6 supersot?-8 supremos ? syncfet? sync-lock? ?* the power franchise ? the right technology for your success? ? tinyboost? tinybuck? tinycalc? tinylogic ? tinyopto? tinypower? tinypwm? tinywire? transic ? trifault detect? truecurrent ? * serdes? uhc ? ultra frfet? unifet? vcx? visualmax? xs? tm ? tm ? tm datasheet identification product status definition advance information formative / in design datasheet contains the design specifications for product development. specifications may change in any manner without notice. preliminary first production datasheet contains preliminary data; supp lementary data will be published at a later date. fairchild semiconductor reserves the ri ght to make changes at any time without notice to improve design. no identification needed full production datasheet contains final specifications. fair child semiconductor reserves the right to make changes at any time without notice to improve the design. obsolete not in production datasheet contains specifications on a product t hat is discontinued by fairchild semiconductor. the datasheet is for reference information only. anti-counterfeiting policy fairchild semiconductor corporation?s anti-counterfeiting policy. fairchild?s anti-counterfeiting policy is also stated on our external website, www.fairchildsemi.com, under sales support . counterfeiting of semiconductor parts is a growing problem in th e industry. all manufactures of semiconductor products are expe riencing counterfeiting of their parts. customers who inadvertently purchase counterfeit parts ex perience many problems such as loss of brand reputation, substa ndard performance, failed application, and increased cost of production and manufacturing dela ys. fairchild is taking strong measures to protect ourselve s and our customers from the proliferation of counterfeit parts. fairchild strongly encourages customers to purchase fairchild parts either directly from fa irchild or from authorized fairchild distributors who are listed by c ountry on our web page cited above. products customers buy either from fairchild directly or fr om authorized fairchild distributors are genuine parts, have full traceability, meet fairchild?s quality standards for handing and storage and provide access to fairchild?s full range of up-to-date technical and product information. fairchild and our authorized distributors will stand behind all warranties and wi ll appropriately address and warranty issues that may arise. fairchild will not provide any warranty coverage or other assistance for parts bought from unau thorized sources. fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors. rev. i55
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